In a multi-core memory circuitry, a precharge and evaluate circuit is usually needed in the read data path to gain performance. The precharge and evaluate circuit of the multi-core memory circuitry needs a keeper circuit in order to hold data on the data path when not driven.
Keeper sizing is very critical and requires numerous stacks in the data path to maintain the sizing. Further, the evaluate circuit has a large resistor-capacitor (RC) network either on the gate or on the drain of a transistor. Data paths being highly resistive add another challenge to the size of the evaluate circuit and limits performance.